As integrated circuits grow ever smaller and faster, delays associated with the wiring, as opposed to the active devices, have become increasingly more important. To reduce said delays it is necessary to reduce the resistance of the wires and/or the capacitance per unit length across the inter-metal dielectrics. Wire widths in integrated circuits have, however, continued to shrink so the electrical conductivity of the wiring material itself has become increasingly more important. Thus, aluminum, which has been the metal of choice since the integrated circuit art began, is now being increasingly replaced by copper.
Similarly, silicon dioxide, which has been the inter-metal dielectric (IMD) of choice since the integrated circuit art began, is now being increasingly replaced by new, low dielectric constant materials. An example of the latter is fluorinated silicon glass (FSG) which typically has a dielectric constant of about 3.5.
As might be expected, integrated circuits having both copper wiring and IMDs of FSG are now in active development at many locations. Before copper could be introduced into integrated circuits, one problem needed to be overcome, namely copper's tendency to be both a fast diffuser as well as a source of recombination centers in silicon. Although a number of materials were known to be effective barriers against copper diffusion at or near room temperature, they could not be relied upon when conventional multi-layering was used because of the difficulty of adequately covering the wiring's edges.
The wiring coverage problem was solved by the introduction of damascene wiring. The term damascene when used in connection with integrated circuit wiring, refers to the fact that a layer has been inlaid within a supporting medium, as opposed to being covered by it. Thus, instead of the wiring being laid down on top of the IMD, a trench is first formed in its surface and this trench then filled with copper. Lining the walls of the trench with a barrier layer prior to filling in with copper then becomes a straightforward procedure.
FIG. 1a is a schematic illustration of a damascene connector. Seen there is an FSG layer 12 on a substrate 11. Via hole 31 was etched through the full thickness of layer 12 so as to expose substrate 11 which, in most cases, would be the upper surface of a partially formed integrated circuit, and then just filled with copper material 44 (after laying down barrier layer 14). The filling step is accomplished by initially over-filling with copper and then removing the excess by means of chemical mechanical polishing (CMP).
Unfortunately, the fluoride ions in the FSG are not very strongly bound and a certain amount of free fluorine is able to react with the copper during the CMP process, resulting in the formation of defect structures 13 at the edges of the filled via hole, as illustrated schematically in FIG. 1b. 
The present invention describes a structure, and process for making it, which overcomes this problem while still supporting copper damascene wiring on a FSG base.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,008,120 (Lee) teaches use of the oxynitride ARC layer as the means for keeping fluoride away from the metal used to fill a via. Although there is an oxide cap over the oxynitride layer early in their process, they go to some trouble to selectively remove it from over the site of the fixture via hole. In U.S. Pat. No. 6,103,601, Lee et al. show how FSG films can be densified by hydrogen ion bombardment. The problem of etching a via hole through the FSG layer, filling it with copper and then planarizing by CMP is not discussed.
In U.S. Pat. No. 6,121,164, Yieh et al. are concerned with reducing stress in FSG layers. One approach they suggest is an overlying USG capping layer. Cu CMP is not part of their process. U.S. Pat. No. 6,130,157 (Liu et al.), and U.S. Pat. No. 6,136,680 (Lai et al.) show related patents while U.S. Pat. No. 6,150,272 (Liu et al.) show Cu CMP with FSG, using an organic layer over the FSG layer.